1. Field of the Invention
This invention relates generally to fabrication of capacitors for semiconductor devices and more particularly to the fabrication of a capacitors and pad contacts for an analog integrated circuit device.
2. Description of the Prior Art
In the fabrication of combined analog and digital integrated circuits it is common to form capacitors over field oxide regions and form MOS FET near by. For the inventors to improve the capacitor performance, higher dielectric constant capacitor SiN (silicon nitride) is deposited over the bottom storage electrode (poly-1) layer and before the interlevel dielectric (ILD).
The inventors have found that the SiN over the polysilicon bottom plate causes Threshold voltage (Vt) uniformity problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,658,821 (Chen et al.) Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage--that discloses a method for the formation of capacitors comprising a polysilicon first capacitor plate, polysilicon oxide dielectric, and a metal second capacitor plate which improves uniformity of capacitance and avoids device damage. More particularly the patent discloses conditioning the polysilicon first capacitor plate by forming a thin layer of polysilicon oxide on the polysilicon followed by removal of the polysilicon oxide using a buffered oxide etch or a dry anisotropic etch. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.
U.S. Pat. No. 4,922,312 (Coleman et al.) DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor and U.S. Pat. No. 5,098,192 (Colemen et al.) and U.S. Pat. No. 5,244,825(U.S. Pat. No. 5,098,192 (Colemen et al.)--teach methods for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.
However, further improvements can be made to improve the VT uniformity.